Simple TCL project starter

# constants
set origin_dir "/home/hbucher"
set proj_name "project_6"

# create project
create_project $proj_name $origin_dir/$proj_name -part xc7z010clg400-1
set_property board_part digilentinc.com:zybo:part0:1.0 [current_project]
set_property target_language VHDL [current_project]

# Create design
create_bd_design "design_1"
update_compile_order -fileset sources_1

# Add PS, apply defaults
create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" }  [get_bd_cells processing_system7_0]

# Create GPIO and add buttons and switches
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0
apply_board_connection -board_interface "btns_4bits" -ip_intf "axi_gpio_0/GPIO" -diagram "design_1"
apply_board_connection -board_interface "sws_4bits" -ip_intf "axi_gpio_0/GPIO2" -diagram "design_1"
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "New AXI Interconnect" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" }  [get_bd_intf_pins axi_gpio_0/S_AXI]

# Create another GPIO and add leds
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1
apply_board_connection -board_interface "leds_4bits" -ip_intf "axi_gpio_1/GPIO" -diagram "design_1"
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "/ps7_0_axi_periph" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" }  [get_bd_intf_pins axi_gpio_1/S_AXI]

# Make wrapper
validate_bd_design
make_wrapper -files [get_files $origin_dir/$proj_name/$proj_name.srcs/sources_1/bd/design_1/design_1.bd] -top
add_files -norecurse $origin_dir/$proj_name/$proj_name.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd

# Make bitstream
launch_runs impl_1 -to_step write_bitstream -jobs 4

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