# constants
set origin_dir "/home/hbucher"
set proj_name "project_6"
# create project
create_project $proj_name $origin_dir/$proj_name -part xc7z010clg400-1
set_property board_part digilentinc.com:zybo:part0:1.0 [current_project]
set_property target_language VHDL [current_project]
# Create design
create_bd_design "design_1"
update_compile_order -fileset sources_1
# Add PS, apply defaults
create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 ...